The present invention relates to a backplane structure for a computer incorporating bus lines for cummunication between various sections of the computer.
Most computers consist generally of a control section, a memory section for storage of data and program instructions, a buffer or register section for temporary data storage, and a functional unit section for performing operations. Communication between various parts of the computer and between the computer and peripheral devices takes place on one or more buses devoted to the transfer of data, addresses and control signals. The bus lines may be bi-directional or unidirectional. The use of a shared bus vastly simplifies interconnection of units but must be designed with care to avoid signal collision and interference problems.
In most computers the various circuit boards containing the computer components are mounted in card edge connectors on a suitable backplane, with lines running across the backplane to connect corresponding bus pins on all the cards for signal communication between the respective components. With computers of increasing size, speed and complexity the problems of interconnecting the various units are multiplied, with the numbers of lines required for signal transfer increasing in computers superpositioning scalar and vector operations to enormous numbers which are outside the range of present day high density card edge connectors. Thus the computer architect may find that the card edge connector has insufficient pins to provide the number of separate bus lines required. For example, the standard scalar machine with two to four 32-bit buses on a single backplane practically saturates the physical and electrical capabilities of the backplane; such a backplane is definitely insufficient for an architecture requiring the equivalent of eighteen 64-bit buses. Also, there is a minimum spacing allowable between adjacent bus lines below which interference can occur between the lines. Where large numbers of bus lines are needed for signal transfer there may be insufficient space available on the back plane to provide the necessary number of lines. Added to this is the fact that the line length is also limited by the speed of signal transfer necessary for the particular machine.
Some of these problems have been solved in the past by point to point wiring between the circuit boards, but this results in large machines with miles of wiring and resultant reduction in speed of data transfer. Manufacturing of point to point wiring is also a very slow and tedious operation, substantially increasing manufacturing costs of such machines and making production relatively slow. The backplane of such machines is a mass of wiring, difficult to install and maintain, as compared to the relatively easy assembly and maintenance of an integral bus backplane structure.
Recently, a category of computer has emerged that realizes highly efficient computing by provision of an architecture containing both scalar and vector capabilties. The integration of scalar and vector structures into a single construct is referred to as superposition. Superposition results in a computing machine that can use software compatible with existing scalar and vector systems to achieve the speed inherent in vector processing, while enjoying the precision and flexibiltiy of scalar processing.
Machines which superposition vector and scalar functions are referred to popularly as "super computers." The best example of this type of machine is found in the line of products available from Cray Research, Inc., Chippewa Falls, Minnesota. These computers superposition scalar and vector operations by employing concurrent scalar and vector processes to calculate, for example, starting and ending indices for vector data structures, and vector techniques to perform memory references and functional operations on the indexed vector structures.
Typically, a computer which superpositions scalar and vector operations has a main memory consisting of a plurality of interleaved individual memory units in which multiple units can be concurrently accessed by simultaneous processes for storage or retrieval. Superposition also requires the provision of a plurality of functional units, each for performing a specified arithmetic or logical function. Normally, the functional units have pipelined structures which permit them to receive a set of operands for one operation while still processing a set of operands for a previous operation. Such functional units can be used for vector operations, as well as for performance of floating point operations on scalar operands. Finally, the architecture of a superpositioning computer typically includes a bank of scalar and vector registers that act as buffers or caches between memory and functional units. the primary purpose of positioning buffer registers between memory and functional units is to reduce memory access time in scalar operations and to increase memory throughput in vector operations.
The Cray X-MP provides the most current example of a computer which superposes scalar and vector operations and which has an architecture including the elements previously discussed. In this machine, connectivity between the architectural blocks is provided on unidirectional data paths that are physically implemented using point-to-point wiring.
In the prior art, the interconnection technology of superpositioning computers has not incorporated the bi-directional databus. Such a databus structure in its present form is inapplicable to the superpositioning computer because it does not permit the scalar and vector processes to have independent, but concurrent, paths to and from memory. Such an independent memory data connection is necessary because it permits the scalar section to fully perform all index calculations without interfering with the concurrently-operating vector processes that require the indices. Further, the traditional bi-directional databus forces the memory, general purpose registers, and ALU of scalar machines to use the same data for data transfers, thus removing the buffers functionally and physically from between the memory and ALU. An architecture that does not contain independent data paths does away with the response time and throughput benefits provided by positioning scalar and vector registers between the memory and the functional units.
Thus, there is an evident need in the field of superpositioning computers to reduce the amount of physical resources required to support data interconnection, which need is not fulfilled by a traditional databus structure upon which all data transfers in a computer are made.
It is therefore the primary objective of the present invention to advance a backplane structure for use in a computer which superposes scalar and vector operations, which will reduce the physical dimensions of the data interconnection resources of the computer, yet which will retain the benefits of quick response time and efficient throughput realized by the computer's architecture.
It is also an object of the present invention to provide an improved backplane structure for interconnection of units in a computer superimposing scalar and vector operations.